The bitcells of static random access memory (SRAM) devices consume leakage power even when not in use. This leakage or ‘standby’ power is often a large component of the total power consumption in modern system-on-chip (SoC) devices that feature densely packed devices of various types, since such devices often include a significant amount of onboard SRAM. Various efficiency techniques, such as SRAM sleep modes have been developed as a viable solution to reduce SRAM standby power consumption. Such techniques can be either passive or active, with active control generally offering superior power savings and more reliable array stand-by voltage (Vsleep) than passive control.
Various techniques have been developed to control sleep modes in SRAM devices and reduce the standby power consumed by these devices. One example sleep mode method that is currently used interrupts the memory voltage regulator during a memory access, thus driving the bias of the output device and the input to the regulator to supply rails. This disturbance places the VDDA level above the bitcell retention voltage after an access while the voltage regulator output returns to the targeted level. In such present systems, the regulator amplifier must slew its output back to the proper bias point after an access operation, and at least one amplifier is required for every section of the memory array that is to be independently revived. This means that at least one regulator amplifier must be provided for every sub-array or independent portion of the SRAM memory. This present solution tightly constrains the design of the array and amplifier, and requires the usage of a significant amount of space and power.
In general, SRAM array sleep regulators need to track only temperature-induced leakage changes, and so they can have a low slew rate for low standby current. Sustained SRAM wake operations with elevated VDDA, however, may supply charges to VDDA faster than they leak away, thus lowering the regulator output current. When operations cease and VDDA drops rapidly, the regulator is unable to keep up, resulting in VDDA undershoot and a threat to SRAM data retention. Using bypass capacitance to mitigate this problem is possible, but is generally not feasible due to the large area needed.
The subject matter discussed in the background section should not be assumed to be prior art merely as a result of its mention in the background section. Similarly, a problem mentioned in the background section or associated with the subject matter of the background section should not be assumed to have been previously recognized in the prior art. The subject matter in the background section merely represents different approaches.